This invention relates to a pattern generator for generating an address pattern for testing a memory such as, for example, a random access memory.
A random access memory permits arbitrary read and write at any address, as is well-known in the art, but this kind of memory may in some cases be fabricated with some memory cells remaining defective, due, for example, to a defect of a semiconductor substrate. The defective cells cause various malfunctions in the operation of the memory. The malfunction that data can neither be written in nor read from the memory can easily be found out; but, sometimes a malfunction occurs wherein, although the memory operates normally when accessed in the sequential order of arrangement of the cells, it does not operate normally when accessed from a remote address. To detect such a malfunction, it is necessary to operate the memory cells in various patterns possible in actual working conditions and to check whether the operation is normal or not. To this end, there has heretofore been proposed a pattern generator to generate the test patterns necessary for various tests, such as walking, galloping and so forth.
A memory is usually adapted so that each particular memory cell is selected by a row address pattern and a column address pattern. The conventional address pattern generator has a row address pattern generator and a column address pattern generator; these address pattern generators are each provided with one or more address operating circuits; and these address operating circuits each have fixedly connected thereto two fixed registers respectively having loaded therein an initial value or boundary value and an operand. The initial value corresponds to the address of the memory cell which is accessed first when starting a test. The boundary value is a final value of a row address, for example, in the case where the column address is fixed where row addresses are successively changed and the column address is changed only when a certain row address is reached. The operand is a constant number by which an address is increased.
In the prior art address pattern generator, since the two fixed registers are individually connected to the address operating circuit, as described above, modification of a changing format of the address pattern generated calls for modification of the contents of the fixed registers; especially, in the case of an address pattern changing complicatedly, it is necessary to modify the contents of the fixed registers during the test. This modification requires at least one operation cycle of the pattern generator, and during the modification, the test of the memory is interrupted. That is to say, there occurs what is called a dummy cycle, and as a result of this, the time for the test increases accordingly. During interruption of the test, the content of the memory may sometimes vary, making the test incorrect. Further, in the conventional address pattern generator, the row and column address pattern generators are provided independently for producing row and column address patterns respectively. Therefore, for the address operation, arithmetic circuits are required which have a scale of the number of bits of each of the row and column address patterns, and in the case of dividing the memory under test into a plurality of memory parts and successively accessing the same addresses within the respective memory parts, formation of the pattern may become relatively complicated, resulting in a dummy cycle.
An object of this invention is to provide an address pattern generator which is capable of generating even complicated patterns without introducing any dummy cycle.
Another object of this invention is to provide an address pattern generator which is capable of generating complicatedly changing patterns on a relatively small operation scale and with simple operations.